Being an adult means I can afford to buy ten pounds of jellybeans: https://www.jellybelly.com/10-lb-bulk-jelly-beans/c/637
So I got angry at FPGA dev because verilog is a terrible language. I've seen the various higher level languages that generate verilog, but I'd rather have a language that was actually designed for FPGA dev.
How to build such a thing? My first thought is to find a way to generate a netlist easily. What might that be? Some sort of graph description language?
I randomly found https://interestingengineering.com/what-operating-system-is-the-best-choice-for-software-engineers
This article claims Ubuntu has no native support for Linux?
It also claims Linux' proprietary Windows/OS X is expensive? What does that even mean?
Haskell, recurse center, swedish, unicycle
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